 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| CS4340A 24-Bit, 192 kHz Stereo DAC for Audio Features 101 dB Dynamic Range -91 dB THD+N +3.3 V or +5 V Power Supply 50 mW with 3.3 V supply Low Clock Jitter Sensitivity Filtered Line Level Outputs On-Chip Digital De-emphasis for 44.1kHz Popguard(R) Technology for Control of Clicks and Pops Up to 200 kHz Sample Rates Automatic Mode Detection for Sample Rates between 4 and 200 kHz Pin Compatible with the CS4340 Description The CS4340A is a complete stereo digital-to-analog system including digital interpolation, fourth-order deltasigma digital-to-analog conversion, digital de-emphasis and switched capacitor analog filtering. The advantages of this architecture include: ideal differential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and temperature, and a high tolerance to clock jitter. The CS4340A accepts data at all standard audio sample rates up to 192 kHz, consumes very little power, operates over a wide power supply range and is pin compatible with the CS4340, as described in section 3.1. These features are ideal for DVD audio players. ORDERING INFORMATION CS4340A-KS 16-pin SOIC, -10 to 70 C CDB4340A Evaluation Board SCLK RST DEM MUTEC De-emphasis Interpolation Filter Interpolation Filter External Mute Control DAC LRCK SDIN Serial Audio Interface Analog Filter AOUT L DAC Analog Filter AOUTR DIF0 DIF1 MCLK Preliminary Product Information http://www.cirrus.com This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright Cirrus Logic, Inc. 2002 (All Rights Reserved) (c) OCT `02 DS590PP2 1 CS4340A TABLE OF CONTENTS 1. PIN DESCRIPTION ......................................................................................... 4 2. TYPICAL CONNECTION DIAGRAM .............................................................. 5 3. APPLICATIONS .............................................................................................. 6 3.1 Upgrading from the CS4340 to the CS4340A ...................................... 6 3.2 Sample Rate Range/Operational Mode Detect ................................... 6 3.3 System Clocking .................................................................................. 6 3.4 Digital Interface Format ....................................................................... 7 3.5 De-Emphasis ....................................................................................... 8 3.6 Power-up Sequence ............................................................................ 9 3.7 Popguard(R) Transient Control .............................................................. 9 3.7.1 Power-up .................................................................................... 9 3.7.2 Power-down ............................................................................... 9 3.7.3 Discharge Time .......................................................................... 9 3.8 Mute Control ...................................................................................... 10 3.9 Grounding and Power Supply Arrangements .................................... 10 4. CHARACTERISTICS AND SPECIFICATIONS ............................................ 11 ANALOG CHARACTERISTICS (CS4340A-KS) ........................................ 11 COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE.............................................. 13 SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE ............. 16 DC ELECTRICAL CHARACTERISTICS ................................................... 17 DIGITAL INTERFACE SPECIFICATIONS ................................................ 17 DIGITAL INPUT CHARACTERISTICS ...................................................... 17 THERMAL CHARACTERISTICS AND SPECIFICATIONS ....................... 17 RECOMMENDED OPERATING SPECIFICATION ................................. 18 ABSOLUTE MAXIMUM RATINGS ............................................................ 18 5. PARAMETER DEFINITIONS ........................................................................ 19 6. REFERENCES .............................................................................................. 19 7. PACKAGE DIMENSIONS ............................................................................. 20 Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to http://www.cirrus.com/corporate/contacts/sales.cfm IMPORTANT NOTICE "Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. "Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights of the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign Trade Law and is to be exported or taken out of the PRC. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. 2 DS590PP2 CS4340A LIST OF FIGURES Figure 1. Typical Connection Diagram............................................................................................ 5 Figure 2. CS4340A Format 0 - I2S up to 24-Bit Data ...................................................................... 7 Figure 3. CS4340A Format 1 - Left Justified up to 24-Bit Data....................................................... 8 Figure 4. CS4340A Format 2 - Right Justified, 24-Bit Data ............................................................ 8 Figure 5. CS4340A Format 3 - Right Justified, 16-Bit Data ............................................................ 8 Figure 6. De-Emphasis Curve......................................................................................................... 8 Figure 7. Output Test Load ........................................................................................................... 12 Figure 8. Maximum Loading.......................................................................................................... 12 Figure 9. Single-Speed Stopband Rejection ................................................................................. 14 Figure 10. Single-Speed Transition Band ..................................................................................... 14 Figure 11. Single-Speed Transition Band (Detail)......................................................................... 14 Figure 12. Single-Speed Passband Ripple ................................................................................... 14 Figure 13. Double-Speed Stopband Rejection.............................................................................. 14 Figure 14. Double-Speed Transition Band.................................................................................... 14 Figure 15. Double-Speed Transition Band (Detail) ....................................................................... 15 Figure 16. Double-Speed Passband Ripple.................................................................................. 15 Figure 17. Serial Input Timing ....................................................................................................... 16 LIST OF TABLES Table 1. CS4340A Auto-Detect....................................................................................................... 6 Table 2. Single-Speed Mode Standard Frequencies ...................................................................... 7 Table 3. Double-Speed Mode Standard Frequencies..................................................................... 7 Table 4. Quad-Speed Mode Standard Frequencies ....................................................................... 7 Table 5. Digital Interface Format - DIF1 and DIF0 .......................................................................... 7 Table 6. De-Emphasis Control ........................................................................................................ 8 DS590PP2 3 CS4340A 1. PIN DESCRIPTION RST SDIN SCLK LRCK MCLK DIF1 DIF0 DEM 1 2 3 4 5 6 7 16 15 14 13 12 11 10 MUTEC AOUTL VA AGND AOUTR REF_GND VQ FILT+ 8 9 Pin Name RST SDIN SCLK LRCK MCLK DIF1 DIF0 DEM FILT+ VQ REF_GND AOUTR AOUTL AGND VA MUTEC # 1 2 3 4 5 6 7 8 9 10 11 12 15 13 14 16 Pin Description Reset (Input) - Powers down device. Serial Audio Data (Input) - Input for two's complement serial audio data. Serial Clock (Input) -Serial clock for the serial audio interface. Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio data line. Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. Digital Interface Format (Input) - Defines the required relationship between the Left Right Clock, Serial Clock and Serial Audio Data. De-emphasis Control (Input) - Selects the standard 15s/50s digital de-emphasis filter response for the 44.1 kHz sample rate. Positive Voltage Reference (Output) - Positive voltage reference for the internal sampling circuits. Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage. Reference Ground (Input) - Ground reference for the internal sampling circuits. Analog Outputs (Output) - The full scale analog output level is specified in the Analog Characteristics table. Analog Ground (Input) Power (Input) - Positive power for the analog, digital and serial audio interface sections. Mute Control (Output) - Control signal for an optional mute circuit. 4 DS590PP2 CS4340A 2. TYPICAL CONNECTION DIAGRAM + 14 VA 0.1 F 1 F +3.3V or +5.0V 2 Serial Audio Data Processor 3 4 SDIN S CLK LR CK CS4340A M UTEC 16 AOUT L 15 3.3 F + 10 k 560 Left Audio O utput C RL Externa l Clock 5 M CLK FILT+ VQ 9 10 .1 F + 1 F 11 + OPTIONAL MUTE CIRCUIT 0.1 F 1 F 6 7 Mode Configuration 8 DIF1 DIF0 REF_GND 3.3 F 12 AOUTR + 10 k 560 DEM 1 RST AGND 13 Right Audio O utput C RL C= R L + 560 4 F S R L 560 Figure 1. Typical Connection Diagram DS590PP2 5 CS4340A 3. APPLICATIONS 3.1 Upgrading from the CS4340 to the CS4340A The CS4340A is pin and functionally compatible with all CS4340 designs, operating at the standard audio sample rates, that use pin 3 as a serial clock input. In addition to the features of the CS4340, the CS4340A supports standard sample rates up to 192 kHz, as well as automatic mode detection for sample rates between 4 and 200 kHz. The automatic mode detection feature allows sample rate changes between single, double and quad-speed modes without external intervention. The CS4340A does not support an internal serial clock mode, sample rates between 50 kHz and 84 kHz or de-emphasis for 32 and 48 kHz, as does the CS4340. 3.2 Sample Rate Range/Operational Mode Detect The device operates in one of three operational modes. It will auto-detect the correct mode when the input sample rate (Fs), defined by the LRCK frequency, falls within one of the ranges illustrated in Table 1. Sample rates outside the specified range for each mode are not supported. Input Sample Rate (FS) 4 kHz - 50 kHz 84 kHz - 100 kHz 170 kHz - 200 kHz MODE Single-Speed Mode Double-Speed Mode Quad-Speed Mode Table 1. CS4340A Auto-Detect 3.3 System Clocking The device requires external generation of the master (MCLK), left/right (LRCK) and serial (SCLK) clocks. The LRCK, defined also as the input sample rate (Fs), must be synchronously derived from the MCLK according to specified ratios. The specified ratios of MCLK to LRCK, along with several standard audio sample rates and the required MCLK frequency, are illustrated in Tables 2-4. 6 DS590PP2 CS4340A Sample Rate (kHz) MCLK (MHz) 256x 8.1920 11.2896 12.2880 384x 12.2880 16.9344 18.4320 512x 16.3840 22.5792 24.5760 768x 24.5760 33.8688 36.8640 32 44.1 48 Table 2. Single-Speed Mode Standard Frequencies Sample Rate (kHz) MCLK (MHz) 192x 256x 16.9344 22.5792 18.4320 24.5760 88.2 96 128x 11.2896 12.2880 384x 33.8688 36.8640 Table 3. Double-Speed Mode Standard Frequencies Sample Rate (kHz) MCLK (MHz) 128x 22.5792 24.5760 192x 33.8688 36.8640 176.4 192 Table 4. Quad-Speed Mode Standard Frequencies 3.4 Digital Interface Format The device will accept audio samples in several digital interface formats as illustrated in Table 5. The desired format is selected via the DIF1 and DIF0 pins. For an illustration of the required relationship between LRCK, SCLK and SDIN, see Figures 2-5. DIF1 0 0 1 1 DIF0 0 1 0 1 DESCRIPTION I2S, up to 24-bit data Left Justified, up to 24-bit data Right Justified, 24-bit Data Right Justified, 16-bit Data FORMAT 0 1 2 3 FIGURE 2 3 4 5 Table 5. Digital Interface Format - DIF1 and DIF0 LR C K Le ft C h a nn el R ig h t C h a nn e l SCLK S D IN MSB -1 -2 -3 -4 -5 + 5 + 4 +3 + 2 + 1 LS B MSB -1 -2 -3 -4 + 5 + 4 + 3 +2 + 1 LS B Figure 2. CS4340A Format 0 - I2S up to 24-Bit Data DS590PP2 7 CS4340A LR C K Le ft C h a nn el R ig h t C h a nn e l SCLK S D IN M SB -1 -2 -3 -4 -5 + 5 + 4 +3 + 2 + 1 LS B M S B -1 -2 -3 -4 +5 +4 +3 +2 +1 LS B Figure 3. CS4340A Format 1 - Left Justified up to 24-Bit Data LR CK L ef t C h a n ne l R ig h t C h a n n el SCLK SDIN 0 23 22 21 20 19 18 7 6 5 4 3 2 1 0 23 22 21 20 19 18 7 6 5 4 3 2 1 0 3 2 c lo cks Figure 4. CS4340A Format 2 - Right Justified, 24-Bit Data LR CK L ef t C h a n ne l R ig h t C h a n n el S CLK S DIN 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 2 c lo cks Figure 5. CS4340A Format 3 - Right Justified, 16-Bit Data 3.5 De-Emphasis The device includes on-chip digital de-emphasis. Figure 6 shows the de-emphasis curve for Fs equal to 44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs. Please see Table 6 for the desired de-emphasis control. Gain dB T1=50 s 0dB DEM DESCRIPTION T2 = 15 s -10dB 0 1 Disabled 44.1 kHz Table 6. De-Emphasis Control F1 3.183 kHz F2 Frequency 10.61 kHz Figure 6. De-Emphasis Curve 8 DS590PP2 CS4340A 3.6 Power-up Sequence Reliable power-up can be accomplished by keeping the device in reset until the power supply and configuration pins are stable, and the clocks are locked to the appropriate frequencies discussed in section 3.3. It is also recommended that reset be enabled if the analog supply drops below the minimum specified operating voltage to prevent power glitch related issues. 3.7 Popguard(R) Transient Control The CS4340A uses Popguard(R) technology to minimize the effects of output transients during power-up and power-down. This technology, when used with external DC-blocking capacitors in series with the audio outputs, minimizes the audio transients commonly produced by single-ended single-supply converters. It is activated inside the DAC when RST is enabled/disabled and requires no other external control, aside from choosing the appropriate DC-blocking capacitors. 3.7.1 Power-up When the device is initially powered-up, the audio outputs, AOUTL and AOUTR, are clamped to AGND. Following a delay of approximately 1000 sample periods, each output begins to ramp toward the quiescent voltage. Approximately 10,000 LRCK cycles later, the outputs reach VQ and audio output begins. This gradual voltage ramping allows time for the external DC-blocking capacitors to charge to the quiescent voltage, minimizing the power-up transient. 3.7.2 Power-down To prevent transients at power-down, the device must first enter its power-down state by enabling RST. When this occurs, audio output ceases and the internal output buffers are disconnected from AOUTL and AOUTR. In their place, a soft-start current sink is substituted which allows the DCblocking capacitors to slowly discharge. Once this charge is dissipated, the power to the device may be turned off and the system is ready for the next power-on. 3.7.3 Discharge Time To prevent an audio transient at the next power-on, it is necessary to ensure that the DC-blocking capacitors have fully discharged before turning on the power or exiting the power-down state. If not, a transient will occur when the audio outputs are initially clamped to AGND. The time that the device must remain in the power-down state is related to the value of the DC-blocking capacitance. For example, with a 3.3 F capacitor, the minimum power-down time will be approximately 0.4 seconds. DS590PP2 9 CS4340A 3.8 Mute Control The Mute Control pin goes high during power-up initialization, reset, or if the MCLK to LRCK ratio is incorrect. The pin will also go high following the reception of 8192 consecutive audio samples of static 0 or -1 on both the left and right channels. A single sample of non-zero data on either channel will cause the Mute Control pin to go low. This pin is intended to be used as a control for an external mute circuit to prevent the clicks and pops that can occur in any single-ended single supply system. Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit. See the CDB4340A data sheet for a suggested mute circuit. 3.9 Grounding and Power Supply Arrangements As with any high resolution converter, the CS4340A requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 1 shows the recommended power arrangements, with VA connected to a clean supply. If the ground planes are split between digital ground and analog ground, REF_GND & AGND should be connected to the analog ground plane. Decoupling capacitors should be as close to the DAC as possible, with the low value ceramic capacitor being the closest. To further minimize impedance, these capacitors should be located on the same layer as the DAC. All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.1 F, must be positioned to minimize the electrical path from FILT+ and REF_GND (as well as VQ and REF_GND), and should also be located on the same layer as the DAC. The CDB4340A evaluation board demonstrates the optimum layout and power supply arrangements. 10 DS590PP2 CS4340A 4. CHARACTERISTICS AND SPECIFICATIONS Typical performance characteristics are derived from measurements taken at TA = 25 C, VA = 3.3 V and VA = 5.0 V. Min/Max performance characteristics are guaranteed over the specified operating temperature and voltages.) ANALOG CHARACTERISTICS (CS4340A-KS) (Test conditions (unless otherwise specified): Input test signal is a 997 Hz sine wave; measurement bandwidth is 10 Hz to 20 kHz; test load RL = 10 k, CL = 10 pF (see Figure 7).) VA = 5.0V Parameter Single-Speed Mode Dynamic Range 18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit Fs = 48kHz (Note 1) VA = 3.3V Max Min Typ Max Unit Min Typ unweighted A-Weighted unweighted A-Weighted (Note 1) 92 95 - 98 101 92 95 -91 -78 -38 -90 -72 -32 -85 - 88 91 - 94 97 92 95 -94 -74 -34 -91 -72 -32 -88 - dB dB dB dB dB dB dB dB dB dB 16-Bit 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB Fs = 96kHz (Note 1) Double-Speed Mode Dynamic Range 18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit unweighted A-Weighted unweighted A-Weighted (Note 1) 92 95 - 98 101 92 95 -91 -78 -38 -90 -72 -32 -85 - 88 91 - 94 97 92 95 -94 -74 -34 -91 -72 -32 -88 - dB dB dB dB dB dB dB dB dB dB 16-Bit 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB Fs = 192kHz (Note 1) Quad-Speed Mode Dynamic Range 18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit unweighted A-Weighted unweighted A-Weighted (Note 1) 92 95 - 98 101 92 95 -91 -78 -38 -90 -72 -32 -85 - 88 91 - 94 97 92 95 -94 -74 -34 -91 -72 -32 -88 - dB dB dB dB dB dB dB dB dB dB 16-Bit 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB DS590PP2 11 CS4340A ANALOG CHARACTERISTICS (CS4340A-KS) (Continued) Parameters Dynamic Performance for All Modes Interchannel Isolation (1 kHz) DC Accuracy Interchannel Gain Mismatch Gain Drift Analog Output Characteristics and Specifications Full Scale Output Voltage Output Impedance Minimum AC-Load Resistance Maximum Load Capacitance (Note 2) (Note 2) Symbol Min 0.6*VA - Typ 102 0.1 100 0.7*VA 100 3 100 Max 0.8*VA - Units dB dB ppm/C Vpp k pF RL CL - Notes: 1. One-half LSB of triangular PDF dither is added to data. 2. Refer to Figure 8. . 125 Capacitive Load -- C L (pF) 3.3 F AOUTx + V out R L C L 100 75 50 25 Safe Operating Region AGND 2.5 3 5 10 15 20 Resistive Load -- RL (k ) Figure 7. Output Test Load Figure 8. Maximum Loading 12 DS590PP2 CS4340A COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (The filter characteristics and the X-axis of the response plots have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs.) Parameter Single-Speed Mode - (4 kHz to 50 kHz sample rates) Passband to -0.05 dB corner to -3 dB corner Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay Passband Group Delay Deviation De-emphasis Error (Relative to 1 kHz) (Note 4) (Note 3) Min Typ Max Unit 0 0 -0.02 0.5465 50 - 9/Fs 0.36/Fs - 0.4535 0.4998 +0.08 +0.05/-0.14 Fs Fs dB Fs dB s s dB 0 - 20 kHz Fs = 44.1 kHz Double-Speed Mode - (84 kHz to 100 kHz sample rates) Passband to -0.1 dB corner to -3 dB corner Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay Passband Group Delay Deviation 0 - 40 kHz 0 - 20 kHz (Note 3) 0 0 -0.06 0.577 55 -1 - 4/Fs 1.39/Fs 0.23/Fs 3/Fs 0.4621 0.4982 +0.2 0 - Fs Fs dB Fs dB s s s dB s Quad-Speed Mode - (170 kHz to 200 kHz sample rates) Frequency Response 10 Hz to 20 kHz Group Delay Notes: 3. For Single-Speed Mode, the measurement bandwidth is 0.5465 Fs to 3 Fs. For Double-Speed Mode, the measurement bandwidth is 0.577 Fs to 1.4 Fs. 4. De-emphasis is only available in Single-Speed Mode. DS590PP2 13 CS4340A Figure 9. Single-Speed Stopband Rejection Figure 10. Single-Speed Transition Band Figure 11. Single-Speed Transition Band (Detail) Figure 12. Single-Speed Passband Ripple Figure 13. Double-Speed Stopband Rejection Figure 14. Double-Speed Transition Band 14 DS590PP2 CS4340A Figure 15. Double-Speed Transition Band (Detail) Figure 16. Double-Speed Passband Ripple DS590PP2 15 CS4340A SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE Parameters MCLK Frequency MCLK Duty Cycle Input Sample Rate (Note 5) Symbol Min 1.024 45 Max 38.4 55 50 100 200 60 128xFs 64xFs MCLK ----------------2 Units MHz % kHz kHz kHz % Hz Hz Hz ns ns ns ns ns ns Single-Speed Mode Double-Speed Mode Quad-Speed Mode Fs Fs Fs 4 84 170 40 LRCK Duty Cycle SCLK Frequency Single-Speed Mode Double-Speed Mode Quad-Speed Mode SCLK Pulse Width Low SCLK Pulse Width High SCLK rising to LRCK edge delay SCLK rising to LRCK edge setup time SDIN valid to SCLK rising setup time SCLK rising to SDIN hold time tsclkl tsclkh tslrd tslrs tsdlrs tsdh 20 20 20 20 20 20 - Notes: 5. Speed mode is detected automatically, based on the input sample rate. LR C K t t slrd slrs t sc lk l t sclk h S C LK t t sd lrs sdh S D IN Figure 17. Serial Input Timing 16 DS590PP2 CS4340A DC ELECTRICAL CHARACTERISTICS Parameters Normal Operation (Note 6) Power Supply Current Power Dissipation Power-down Mode (Note 7) Power Supply Current Power Dissipation All Modes of Operation Power Supply Rejection Ratio (Note 8) VQ Nominal Voltage Output Impedance Maximum allowable DC current source/sink Filt+ Nominal Voltage Output Impedance Maximum allowable DC current source/sink MUTEC Low-Level Output Voltage MUTEC High-Level Output Voltage Maximum MUTEC Drive Current 1 kHz 60 Hz PSRR 60 40 0.5*VA 250 0.01 VA 250 0.01 0 VA 3 dB dB V VA = 5.0V VA = 3.3V VA = 5.0V VA = 3.3V IA 60 35 0.3 0.1 A A mW mW VA = 5.0V VA = 3.3V VA = 5.0V VA = 3.3V IA 18 15 90 50 25 20 125 100 mA mA mW mW (AGND = 0V; all voltages with respect to AGND.) Symbol Min Typ Max Units k mA V k mA V V mA DIGITAL INTERFACE SPECIFICATIONS Parameters 3.3 V Logic (2.7 V to 3.6 V DC Supply) High-Level Input Voltage Low-Level Input Voltage 5.0 V Logic (4.5 V to 5.5 V DC Supply) High-Level Input Voltage Low-Level Input Voltage (GND = 0 V; all voltages with respect to GND.) Symbol VIH VIL VIH VIL Min 2.0 2.0 Max 0.8 0.8 Units V V V V DIGITAL INPUT CHARACTERISTICS (AGND = 0V; all voltages with respect to AGND.) Parameters Input Leakage Current Input Capacitance Symbol Iin Min Typ 8 Max 10 Units A pF THERMAL CHARACTERISTICS AND SPECIFICATIONS Parameters Package Thermal Resistance (multi-layer boards) Ambient Operating Temperature (Power Applied) Symbol JA TA Min -10 Typ 74 Max +70 Units C/Watt C DS590PP2 17 CS4340A RECOMMENDED OPERATING SPECIFICATION Parameters DC Power Supply 3.3 V Nominal 5.0 V Nominal VA 2.7 4.5 3.3 5 3.6 5.5 V V Symbol Min Typ Max Units (AGND = 0 V; all voltages with respect to AGND. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.) Parameters DC Power Supply Input Current Digital Input Voltage Ambient Operating Temperature (power applied) Storage Temperature (Note 9) ABSOLUTE MAXIMUM RATINGS Symbol VA Iin VIND TA Tstg Min -0.3 -0.3 -55 -65 Max 6.0 10 VA+0.4 125 150 Units V mA V C C Notes: 6. Normal operation is defined as RST = HI with a 997 Hz, 0dBFS input sampled at the highest Fs for each speed mode, and open outputs, unless otherwise specified. 7. Power Down Mode is defined as RST = LO with all clocks and data lines held static. 8. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figure 1. Increasing the capacitance will also increase the PSRR. 9. Any pin except supplies. 18 DS590PP2 CS4340A 5. PARAMETER DEFINITIONS Total Harmonic Distortion + Noise (THD+N) The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10Hz to 20kHz), including distortion components. Expressed in decibels. Dynamic Range The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Drift The change in gain value with temperature. Units in ppm/C. 6. REFERENCES 1) CDB4340A Evaluation Board Datasheet DS590PP2 19 CS4340A 7. PACKAGE DIMENSIONS 16L SOIC (150 MIL BODY) PACKAGE DRAWING E H 1 b c D SEATING PLANE e A1 A L DIM A A1 b C D E e H L MIN 0.053 0.004 0.013 0.0075 0.386 0.150 0.040 0.228 0.016 0 INCHES NOM 0.064 0.006 0.016 0.008 0.390 0.154 0.050 0.236 0.025 4 MAX 0.069 0.010 0.020 0.010 0.394 0.157 0.060 0.244 0.050 8 JEDEC #: MS-012 MIN 1.35 0.10 0.33 0.19 9.80 3.80 1.02 5.80 0.40 0 MILLIMETERS NOM 1.63 0.15 0.41 0.20 9.91 3.90 1.27 6.0 0.64 4 MAX 1.75 0.25 0.51 0.25 10.00 4.00 1.52 6.20 1.27 8 Controling Dimension is Millimeters 20 DS590PP2 |
Price & Availability of CS4340A-KS
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |